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sdram_vhdl_lattice.rar
- lattice sdram 控制器VHDL源代码
sdram_vhd_134.zip
- Xilinx Sdram控制器VHDL源代码
EvsStore
- 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
sdramusevhdl
- sdram的vhdl实现 本文介绍了sdram的控制时序特征,并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
CCD
- 本设计主要用来进行图像采集处理,通过摄像头采集图像信息,经过插值算法后存储到外部SDRAM,然后读取图像数据,进行边缘滤波处理后经VGA输出到屏幕上。-This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and th
ddr
- DDR SDRAM 控制器 VHDL代码,可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
XAPP134_SDRAM_VHDL
- XAPP134 SDRAM VHDL design file
mt48lc4m16a2
- 模拟micron的sdram的 VHDL 代码,用于验证自己的sdram控制器。-Micron sdram the VHDL simulation of the code used to validate their sdram controller.
RED--PCI-5.0
- 使用PCI9054作为接口芯片,通过FPGA实现PCI9054,SDRAM和AD之间的连接,本程序是以此为目的编写的.-PCI9054 interface chip used as a through FPGA implementation PCI9054, SDRAM, and the connection between AD, the program is prepared for this purpose.
source
- SDRAM控制器源代码,是ALTERA公司的IP源核,很好很强大-SDRAM controller source code, very very strong
SDR_SDRAM_IP
- SDR SDRAM 控制器,Altera官网重要资料。内涵说明文档,和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
model
- 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
sdr-sdram-controller-source-code
- altera 公司sdr sdram 控制器源码,是VHDL的,大家选择下载-The altera sdr sdram controller source, the VHDL, we choose to download
DDR-SDRAM
- ddr sdram 控制器的源代码,内有vhdl和verilog。-DDR SDRAM controller
sdram-control
- 基于FPGA的SDRAM读写控制程序,由VHDL语言编写-FPGA-based SDRAM read and write control program, by the VHDL language
SDRAM
- 用XilinxSC1500控制SDRAM的一段VHDL代码。控制SDRAM每个时钟内输出地址所在的一个数据。-For some VHDL code with XilinxSC1500 Control SDRAM. Control SDRAM Each clock output address where a data.
vhdl-Language-routine-highlights
- 工程中常用的VHDL控制模块,包括三态门,SDRAM,FIFO,PLL,RAM,FIlter等模块,非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
SDRAM
- SDRAM控制器的VHDL语言描述及仿真-SDRAM controller
ddr_sdram
- 包含ddr_sdr_conf_pkg.vhd,reset.vhd,ddr_dcm.vhd,user_if.vhd,ddr_sdram.vhd,Mt46v16m16.vhd以及仿真TB文件;设计采用Virtex ii系列芯片,DDR_SDRAM型号为Mt46v16m16,可用于进行DDR控制的初步学习使用;通过细致了解并进行逻辑控制,可深入理解DDR芯片内部构造; 支持133MHz系统时钟频率,突发长度为2,可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作,较
Datasheet_HY5PS1G431C(L)FP_HYNIX
- Datasheet_HY5PS1G431C(L)FP_HYNIX